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1 www.semtech.com sc45 1 0 high performance synchronous buck contr oller with r ef erence t rac king power management united states patent #6,441,597 features applications revision: jan 07, 2005 typical application circuit description u synchronous buck operation with current sink or source without loss of regulation u output can track internal or external reference u buffered reference output from external reference u combi-sense mode lossless current sensing u 2.5v to 16v operation with 4.75v minimum v cc u direct drive for high side n-channel mosfets with diode and capacitor bootstrap u undervoltage lockout, soft start, enable and power good functions u fast transient response with external compensation u current mode control with transconductance error amplifier u programmable oscillator frequency with external sync u externally referenced buck convertors u ddr memory terminators u point of use power supplies the SC4510 can be configured as a synchronous buck convertor capable of sourcing and sinking current from load without losing output regulation. the output can be set to track an internal reference or an external voltage. the actual reference used by the error amplifier is buffered and brought out as a reference. it is the ideal choice for externally referenced or tracking buck convertors such as those for ddr memory applications. the controller is also designed for point of use dc-dc convertors with 2.5-16v power sources with a vcc of 4.5v or higher. soft start, current limit, programmable oscillator and external compensation functions are provided to ensure high degree of integration and low external component count. semetch?s patented combi-sense? technique is utilised for lossless current sening and maximising efficiency. both high and low side mosfet drivers are built in and rated for substantial peak currents to minimise switching losses. the SC4510 is offered in a space saving tssop-20 package. c1 c7 c2 c6 c11 r3 r7 r6 q1 q2 l1 refout pgood sync d1 c8 c12 rtn r5 c10 c5 c4 c3 vout r2 0.5v min ext ref int ref rtn 15v max c9 c13 vin 14 pvcc 8 avcc 7 pgnd 10 gdl 9 gdh 11 bst 12 agnd 20 comp 18 in- 17 ss/en 15 rosc 16 refin 2 cs+ 4 vpn 13 ref 1 refout 3 cs- 5 pgood 6 sync 19 u1 SC4510 r1 r4 in+ vin
2 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management absolute maximum ratings electrical characteristics parameter symbol test conditions min typ max unit power supply operating current no load on gdl and gdh 8 12 ma analog supply input avcc vin > 2.5v 4.75 16 v drive supply input pvcc vin > 2.5v 4.75 16 v convertor power input vin 2.5 16 v undervoltage lockout start threshold avcc min 4.2 4.5 4.7 v uvlo hysteresis avcc hyst 0.2 v soft start and shudown charge current i sschg 2 a discharge current i ssdis 1 a output enable threshold v enth 2.0 v shutdown threshold v ssth 0.6 v parameter symbol maximum units bst, gdh to pgnd -0.3 to 32 (steady state) v -0.3 to 40 (for < 10ns @ freq. < 500khz) pvcc, avcc, vin, vpn, gdl to pgnd -0.3 to 16 v pgnd to agnd 0.3 v cs + to agnd -0.3 to avcc v comp, in-, refin, refout, rosc, ss/en to agnd -0.3 to 6 v refin and refout to agnd 0 to 3.0 v gdh source or sink current + 0.75 a gdl source or sink current + 1 a storage temperature range -60 to +150 c junction temperature -40 to +125 c lead temperature ( soldering ) 10 sec. 260 c esd rating ( human body model ) 2 kv unless specified: t a = t j = -40c to +85c, avcc/pvcc = 12v, fosc = 300 khz, ss/en = 5v exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
3 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management electrical characteristics (cont.) parameter symbol test conditions min typ max unit error amplifier input bias current 0.4 0.7 m a input offset voltage 2.5 mv transconductance gain g m output source mode output sink mode 275 375 mw -1 unity gain bandwidth (1) 3 mhz output sink/source current v comp = 2.5v 15 m a buffered reference internal reference v ref -40c to +85c 0.49 0.5 0.51 v line regulation 5v < avcc < 15v 0.02 %/v external reference input range v refin 0.3 3.0 v tracking accuracy v refout with respect to v refin (greater of the two) + 0.5 + 10.0 % mv reference output current i refout 5 ma oscillator and synchronisation frequency range fosc 0.1 1 mhz frequency setting fosc rosc = 221k 270 300 330 khz sync input high voltage 1.5 v sync input low voltage 0.5 v duty cycle maximum duty cycle fosc = 1 mhz 70 % fosc = 300 khz 90 % minimum duty cycle fosc = 100 khz 5 % minimum pulse width fosc = 0.1 to 1 mhz 250 ns current limit current limit sense threshold v cslim output source mode 60 75 90 mv output sink mode -85 -110 -130 mv delay to output (1) t csdly 10 mv overdrive 50 ns unless specified: t a = t j = -40c to +85c, avcc/pvcc = 12v, fosc = 300 khz, ss/en = 5v
4 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management pin configuration ordering information part number package (1) temp. range (t j ) SC4510itstr tssop-20 -40c to +85c SC4510itstrt (2) notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. 1 2 3 4 5 6 7 8 agnd ref top view (20 pin tssop) 13 14 15 16 sync refin comp refout in- cs+ rosc cs- ss/en pgood vin avcc vpn pvcc 9 10 12 bst gdl gdh pgnd 11 18 17 19 20 parameter symbol test conditions min typ max unit power good output overvoltage sense threshold v ovth refin = 2.5v 2.8 v undervoltage sense threshold v uvth refin = 2.5v 2.2 v power good voltage v pg i pg = 5 ma i pg = 2.5 ma output under fault 1.5 0.4 v v output drive high side gate drive i gdh source or sink 1 a low side gate drive i gdl source or sink 1 a dead time between drives 60 90 120 ns rise time c out = 1000 pf 20 ns fall time c out = 1000 pf 20 ns note: (1) guaranteed by design. not tested in production. unless specified: t a = t j = -40c to +85c, avcc/pvcc = 12v, fosc = 300 khz, ss/en = 5v electrical characteristics (cont.)
5 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management pin # pin name pin function 1 ref internal 0.5v bandgap reference 2 refin non inverting input of the error amplifier. can be connected to ref pin or an external voltage such as vddq/2. maximum input range is 3v 3 refout buffered reference output fro external use. tracks the refin voltage 4 cs+ current sense input +ve 5 cs- current sense input -ve. typically connected to the vout end of the output inductor. 6 pgood power good output signal. open collector output goes low under fault and sinks up to 5 ma. monitors the output at thresholds of + 12% with respect to refin voltage. 7 avcc supply voltage for internal analog circuits. 8 pvcc supply voltage for output drivers. bypass with a large ceramic capacitor to pgnd. 9 gdl gate drive output for the low side n-channel mosfet. 10 pgnd power ground for returning the drive currents. 11 gdh gate drive output for the high side n-channel mosfet. 12 bst boost capacitor connection for the high side gate drive. connect an external capacitor and a diode as shown in the typical application circuit. 13 vpn virtual phase node. auxiliary pin used for virtual current sense.connect an rc between this pin and the vout end of the output inductor to sense the integrated current feedback signal. 14 vin input supply for the virtual current sense circuit. this should be at the same potential as the drain of the high side power mosfet. 15 ss/en soft start and enable pin. grounding the pin shuts down the controller. connect a capacitor to soft start the output.the output will start switching when the ss pin voltage goes above 0.5v. 16 rosc connect a resistor to agnd to program the oscillator frequency. 17 in- inverting feedback input for the error amplifier. follows the reference input provided at the refin pin. maximum voltage range is 3v. 18 comp error amplifier output for compensation. 19 sync pin for external synchronisation signal input 20 agnd analog signal ground. return the ground connections of noise sensitive components such as rosc, soft start capacitor, sync signal, feedback resistor chain and feedback compensation components separately to this pin. pin descriptions
6 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management characteristic curves avcc vs bias current 8 8.5 9 9.5 10 10.5 11 11.5 12 4.5 5 6 7 8 9 10 11 12 13 14 15 avcc ibias ma operating frequency vs rosc 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 rosc in kohm freq in khz typical dmax vs operating frequency 70 75 80 85 90 95 100 100 250 400 550 700 850 1000 operating frequency khz typical dmax %
7 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management characteristic curves internal reference vs temperature 498.00 498.50 499.00 499.50 500.00 500.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) internal ref. (mv) current limit vs temperature 71.00 71.50 72.00 72.50 73.00 73.50 74.00 74.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) current limit (mv) max duty cycle vs temperature @ rosc = 220k 93.85 93.90 93.95 94.00 94.05 94.10 94.15 94.20 94.25 94.30 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) max duty cycle (%) frequency vs temperature @ rosc = 220k 297.50 298.00 298.50 299.00 299.50 300.00 300.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) frequency in khz
8 ? 2004 semtech corp. www.semtech.com SC4510 power management block diagram
9 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management application schematic
10 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management introduction the SC4510 is designed to control and drive n-channel mosfet synchronous rectified buck convertors. it has additional features such as reference tracking, buffered refout that make it particularly attractive for tracking output applications such as ddr memories. it can operate the convertor in both the source and sink modes. the switching frequency is programmable to optimize design. the current mode switching regulator section features semtech?s patented combi sense technique for lossless current sensing and provides a hiccup mode overcurrent protection. powering the controller supplies vin, pvcc and avcc from the input source are used to power the SC4510. the avcc and pvcc can be tied to vin supply or can be from separate source to optimise efficiency. the avcc supply provides the bias for the oscillator, pwm switcher, voltage feedback, current sense and the power ok circuitry. pvcc is used to drive the low and high side mosfet gates. minimum operating limit for vin is 2.5v typical. however, pvcc and avcc have higher uvlo limits as explained below. maximum range for all of the input and supply voltages is 16v. startup and enable startup is inhibited until avcc input reaches its uvlo threshold . the uvlo limit is 4.5v typical. when avcc is below the uvlo threshold, the soft start pin is pulled low and output drivers are turned off. the power up sequence is initiated by a 2 ua current source charging the soft start capacitor connected to the ss pin. when the ss pin reaches 0.5v, the convertor will start switching. the reference input of the error amplifier is ramped up with the soft-start signal. the soft start duration is controlled by the value of the ss cap. the soft start pin also functions as an enabler with ttl compatible input thresholds. if the ss/en pin is pulled below 0.6v, the SC4510 is disabled and draws very low current. reference input and buffered output the SC4510 comes with a low level built in reference of 0.5v. the non inverting input of the error amplifier is brought out to provide additional flexibility and output tracking functions. in the basic operation, the ref and refin pins may be shorted together and the output voltage feedback is provided at in - pin. in tracking applications such as ddr memories an external reference may be brought in and applied at refin pin. the range of applicable external voltage is up to 3v. the uv and ov sensing thresholds for pgood output are centered + 12% around refin voltage. the voltage at refin pin is buffered and put out as refout. this output tracks refin accurately within + 10 mv offset or 0.5% of refin, whichever is higher. it can also source up to 5 ma current. the refout output is particularly useful in ddr memory termination applications. oscillator the switching frequency f osc of the SC4510 is set by an external resistor using the following formula: r osc = 66,000 / f osc r osc is in k w and f osc is in khz. the nominal range for the oscillator frequency is from 100 khz to 1 mhz. the maximum duty cycle available at any given frequency is limited by minimum pulse width requirement which is typically 250 ns. this gives a typical dmax of 70% at the highest frequency of 1 mhz or about 90% at 300 khz. the oscillator can be synchronised to an external clock that is nominally faster than the internal frequency set by r osc. the synchronising signal should be ttl compatible, with transitions above 2.0v and below 0.6v. the external voltage level applied should be lower than avcc of the device. gate drivers the low side gate driver is supplied from pvcc and provides a peak source/sink current of 1a. the high side gate drive is capable of sourcing and sinking peak currents of 0.75a. protection logic provides a typical dead time of 90 ns to ensure both the upper and lower mosfets will not turn on simultaneously and cause a shoot through condition. the high side mosfet gate drive can be derived from the pvcc supply using the classical bootstrap technique as illustrated in the applications circuits. a bootstrap capacitor is connected from bst to the phase node while pvcc is connected through a low v f schottky or an ultrafast diode to the bst. this will provide a gate to source voltage approximately equal to the (vcc - vfwd). functional description
11 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management functional description alternately if an external 12v supply is available it can be directly connected between bst and gnd. the actual gate to source voltage of the upper mosfet will then be approximately be equal to (12v - vin). this technique is useful if the input voltage is 5v but a 12v supply is also available in the system. power good monitor the pgood circuitry monitors the fb input of the convertor error amplifier. if the voltage on this input goes above +12% or below -12% of the refin voltage the pgood pin is pulled low. the pgood is an open drain output and can sink up to 5 ma. the pgood pin is held low during the startup sequence. error amplifier the SC4510 is a current mode controller and operates by matching the peak of the sensed inductor current to the output of the voltage error amplifier. the error amplifier is transconductance type and should be compensated accordingly. it has a transconductance gain of 275 mw -1 in the source mode. current is sensed losslessly by taking the weighted average of both the mosfet drops and adding it to the dc voltage drop across the inductor. more information on this patented combi sense technique is provided in the next section. current mode controllers are inherently unstable at duty ratios above 50% and need some form of slope compensation to operate correctly. this slope compensation is built into the architecture of SC4510 where a portion of the ramp is internally added to the current sense signal. the amount of added ramp is optimised and varies with the operating duty cycle. larger duty ratios result in larger ramps being added to the current sense signal. note that the uncorrected current signal is used for overcurrent comparator. the current limit point is unaffected by the slope compensation.
12 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management application information combi-sense operation and current limit effective current sensing is important for the current mode control of power convertors. instead of using the traditional lossy resistive current sense scheme, a novel lossless combi-sense technique is used in SC4510. this semtech proprietary technology has the advantages of 1) lossless current sensing, 2) bigger signal-to-noise ratio, and 3) thermal run-away prevention. the basic structure of the combi-sense is shown in fig.1. where r l is the equivalent resistance of the output inductor. the added r s and c s form the rc branch in ?parallel? with the output inductor for inductor current sensing. this branch works with a small signal totem pole ( q3 and q4 ) integrated in SC4510 in order to improve the signal-to-noise ratio. the base signals vbe3 and vbe4 are designed to closely follow the gate signals vgs1 and vgs2, respectively. ideally, the leading and falling edges of the virtual phase node (vpn) follow that of the phase node (ph) when q1 ~ q4 switch in perfect synchronism. fig.1 the basic structure of combi-sense. when q1 / q3 turn on and q2 / q4 turn off, the equivalent circuit of fig.1 is shown in fig. 2a). where, rds1 is the on- resistance of the top mosfet. the two branches, consisting of { (rds1+rl), l } and { r s , c s }, are in parallel. the dc voltage drop (rds1+rl)i o equals v cs . in this way, the output current is sensed from v cs when (rds1+rl) is known. q1 q2 cin cout rl rload rs vo vin cs vc(t) l il(t) q3 q4 vpn vbe4 vbe3 vgs2 vgs1 pn when q1 / q3 turn off and q2 / q4 turn on, the equivalent circuit of fig.1 becomes the sub-circuit as shown in fig. 2b). where rds2 is the channel resistance of the bottom mosfet. in this case, the branch { r s ,c s } is in parallel with { (rds2+rl), l } and v cs =(rds2+rl)i o . fig.2 a) equivalent sub-circuit. when averaged over a complete cycle, v cs = [d(rds1+rl)+(1-d)(rds2+rl)] i o = [d rds1+(1-d)rds2+rl]i o = r eq i o . d is the operating duty ratio. it is noted that the average dc value in v cs is independent of the value of l , r s and c s . if only the average load current information is needed (such as in average current mode control), this current sensing method is effective without further requirements. cin cout rl rload rs vo vin cs vc(t) l il(t) pn rds1 vpn cin cout rl rload rs vo vin cs vc(t) l il(t) pn rds2 vpn fig.2 b) equivalent sub-circuit.
13 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management in the application circuit, r eq =5.6 m w . however the peak value of the sensed current is not exact for a number of reasons. though the phase node ph and virtual phase node vpn voltages are assumed to be identical, there will be some offset between them which adds to the average value of the current feedback signal. this is particularly true during the switching transitions where rise and fall times of the true phase node are dependent on the power mosfet characteristics. the peak value of the signal also includes the ripple current d i o riding on the output dc current. in addition, the signal level is subject to variations with respect to input and pvcc voltages. the difference between sensed current magnitude and the actual current gets more pronounced for low output voltages where the operating duty is also low. given these differences, some amount of scaling the current sense signal is required to adjust the current limit in most applications. this can be accomplished easily by simple resistor networks and the possible configurations are shown in fig.3. a) when the required current limit value i lm is greater than i lmcp , remove r s3 and solve for for r s2 = r seq and r seq is the parallel combination of r s and r s1 as shown in fig 3). r s2 helps to reduce the offset at the input of current sense amplifier inside SC4510. q1 q2 cin cout rl rload rs vin vo cs vc(t) l il(t) q3 q4 vgs2 vgs1 vpn vbe4 vbe3 pn - + isen 1 2 rs3 rs2 rs1 eq s seq r l c r = in peak current mode control as in SC4510, the voltage ripple on c s is critical for pwm operation. in fact, the peak- to-peak value of the voltage ripple across v cs (denoted as d v cs ) directly affects the signal-to-noise ratio of the pwm operation. in general, smaller d v cs leads to small signal-to- noise ratio and more noise sensitive operation. larger d v cs leads to more circuit (power stage) parameter sensitive operation. a good engineering compromise is to make d v cs ~r eq d i o . where d i o is the peak to peak ripple current in the inductor. the prerequisite for such relation is the so called time constant matching condition when rds1 = rds2, the above approximations become precise equalities. for the example in the application circuit shown on p9 the inductor value is 1 uh, rl = 1.4 m w , rds1 = 11 m w and rds2 = 3 m w since the operating duty ratio is very small the effective rds is determined mostly by rds2. the time constant r s c s should be set close to 0.2 ms. since the effective value of r s is 20 k w // 18 k w = 9.5 k w, c s = 22 nf was chosen . current limit scaling in SC4510, the current limiting is performed on cycle-by- cycle basis. when the voltage difference between cs+ and cs- exceeds 65 mv, the top mosfet duty ratio is clipped in order to limit the output source current. similarly, when the voltage difference between cs- and cs+ exceeds 113 mv, the bottom mosfet duty ratio is clipped in order to limit the sink current. for the configuration in fig.1, the convertor output current limit is set around for the current sourcing mode and for the current sinking mode. application information (contd.) . s s eq c r r l ? , 75 eq lmcp r mv i = eq lmcn r mv i 110 - = fig.3 current limit scaling.
14 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management for simplicity r s2 can be omitted and the current limit can be estimated from in the application circuit the current feedback signal had to be halved to account for variations explained above and ensure that the current limit is at least 20% above nominal at minimum input. b) when the required current limit value i lm is less than i lmcp remove r s1 solve for r s and solve to set the current limit. similar steps and equations apply to the current limit setting and scaling for current sinking mode. overcurrent protection and hiccup mode in addition to the current limit capabilty, SC4510 provides overcurrent protection in case the convertor output is shorted to ground. if this fault condition happens, the controller senses the output voltage via voltage feedback pin in-. when the sensed voltage is below 70% of the normal feedback voltage, the controller shuts down both top and bottom mosfets. at the same time, a current sink of 1 m a discharges the soft start capacitor c ss connected to the ss/en pin. when the capacitor is discharged until its voltage reaches 0.4v, the controller initiates the soft start process. if the short circuit fault persists, the controller shuts down the convertor again when the voltage across the soft start capacitor reaches 3.4v. this hiccup process repeats until the fault condition is removed. under this situation, it is important to make sure that the convertor does not fail. one important parameter is the convertor thermal condition which is directly related to the effective inductor and mosfets current. the effective currents in inductor and mosfets can be estimated using the following equations. application information (contd.) a) the time it takes to discharge the capacitor from 3.4v to 0.4v in the application circuit, c ss = 47 nf and t ssf is calculated as 140 ms. b) the time interval of the soft start process from 0.4v to 3.4v when c ss = 47 nf, t ssr is calculated as 70 ms. notice that during the soft start process, the convertor only starts switching when the voltage at ss/en exceeds 1.3v. then, c) the effective operation time interval this is the interval where the gate drive outputs are active and current builds up in the inductor. the effective inductor current is then it turns out that ileff is independent of the soft start capacitor value and is determined as 0.3 i lmcp . this should lead to a reasonable thermal condition in the convertor hiccup operation. note that ileff calculated is not the true average value of the inductor current since the convertor is still in the soft start mode during the tsso interval. . 1 ) 4 . 0 4 . 3 ( a v c t ss ssf m - = . 2 ) 4 . 0 4 . 3 ( a v c t ss ssr m - = . 2 ) 3 . 1 4 . 3 ( a v c t ss sso m - = . ssr ssf sso lmcp leff t t t i i + = mv v r r r i o s s eq lm 75 3 = + eq s s r l c r = 1 1 75 s r s r s r eq lm mv r i + =
15 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management application information (contd.) pcb layout for SC4510 careful attention to layout requirements is necessary for successful implementation of the SC4510 pwm controller. high switching currents with fast rise and fall times are present in the application and their effect on ground plane voltage differentials must be understood and minimized. a good layout with minimum parasitic loop areas will a) reduce emi b) lower ground injection currents, resulting in electrically ?cleaner? grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. layout guidelines in the following q t and q b denote the high side and low side mosfets respectively. 1) a ground plane should be used. the number and position of ground plane interruptions should be minimised so as not to compromise ground plane integrity. isolated or semi- isolated areas of the ground plane may be deliberately introduced to constrain ground currents into particular paths, such as the output capacitor or the q b source. 2) the high power, high current parts of the circuit should be laid out first. the on time loop formed by the input capacitor cin, the high side fet q t , the output inductor and the output capacitor bank cout must be kept as small as possible. another loop area to minimise is formed by low side fet q b, the output inductor and the output capacitor bank cout during the off period. these loops contain all the high current, fast transition switching. connections should be as wide and as short as possible to minimize loop inductance. 3) the connection between the junction of q t , q b and the output inductor should be a wide trace or copper region. it should be as short as practical. since this connection has fast voltage transitions, keeping this connection short will minimize emi. also keep the phase connection to the ic short. the top fet gate charge currents flow in this trace. 4) the output capacitor cout should be located as close to the load terminals as possible. fast transient load currents are supplied by cout and connections between cout and the load must be kept short with wide copper areas to minimize inductance and resistance. this will improve the transient response to step loads. 5) the SC4510 is best placed over a quiet ground plane area. avoid pulse currents of the cin, q t , q b loop flowing in this area. this analog ground plane should be connected to the power ground plane at a ?quiet? point near the input capacitor. under no circumstance should it be returned to a point inside the cin, q t , q b , cout power ground loops. 6) the SC4510 agnd pin is connected to the separate analog ground plane with minimum lead length . all analog grounding paths including decoupling capacitors, feedback resistors, compensation components, soft start capacitor, frequency and current-limit setting resistors should be connected to the same plane. 7) locate the critical filtering capacitors as close as possible to their respective device. this is particularly true for the current feedback filtering capacitor connected between cs+ and cs-. a high value ceramic capacitor is also recommended between pvcc and pgnd pins close to the device.
16 ? 2004 semtech corp. www.semtech.com sc45 1 0 power management outline drawing - tssop-20 contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 land pattern - tssop-20 l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 20 .004 .169 .251 .173 .255 .007 - 20 0.10 0.65 bsc 6.40 bsc 4.40 6.50 - .177 .259 4.30 6.40 .012 0.19 4.50 6.60 0.30 bxn 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 1 3 2 n e1 bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view (.039) .004 .008 - .024 - - - - 0 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - (1.0) 0.60 - 0.75 0.20 - - - 1.20 1.05 0.15 a b c d e e/2 h plane d e a1 a2 a reference jedec std mo-153, variation ac. 4. inches b n ccc aaa bbb 01 e1 e l l1 e d c a2 a1 dim a min max millimeters min dimensions nom max nom (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1.

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